1. Field of the Invention
The present invention relates to an output circuit, and more particularly, to a dynamic output buffer circuit for performing an impedance matching function and a pre-emphasis function by using input and output signals.
2. Description of the Related Art
In modeling a common conducting wire, the variation of the electrical characteristics of the wire depending on the frequency of the signal flowing through the wire and the length of the wire are to be taken into account. For example, if the signal flowing through the wire has a low frequency, and thus the wavelength of the signal is larger than the length of the wire, then only the resistive and capacitive components of the wire need to be considered in modeling the wire. On the other hand, if the signal flowing through the wire has a high frequency, and thus the wavelength of the signal is far shorter than the length of the wire, then electromagnetic characteristics also are to be considered in modeling the wire. Therefore, under such high frequency conditions, an impedance component, rather than just the resistive component, has to be considered along with the capacitive component. The impedance of a component is generally referred to as the characteristic impedance of the component.
A conductive line, or metal line, is physically connected between semiconductor chips or systems to transfer signals. The characteristic impedance of the metal line is assumed to be Zo. If the input impedances of the semiconductor chips and the systems connected by the metal line do not match the characteristic impedance Zo of the metal line, then impedance matching is not achieved, and signal reflection can occur. A reflected signal interferes with the original signal, altering the characteristics of input and output signals.
Inter symbol interference (ISI) occurs when a signal is applied before the previous signal reaches a desired voltage, and thus the signal is influenced by the previous signal. ISI generally occurs when a signal has a high frequency, i.e. a short wavelength.
In order to reduce signal refection and ISI in response to a frequency of a transmitted/received signal, an impedance matching circuit and a pre-emphasis circuit are used. The impedance matching circuit is used to match the output impedance of an output terminal of a semiconductor chip to the characteristic impedance Zo of the metal line. The pre-emphasis circuit is used to amplify the edges of a transmitting signal, thereby reducing ISI.
FIG. 1 illustrates an impedance matching circuit between two chips.
Referring to FIG. 1, a metal line connects two chips Chip I and Chip II, and has a characteristic impedance Zo. The output impedance Zout of the first chip Chip I and the input impedance Zin of the second chip Chip II are adjusted to coincide with the characteristic impedance Zo of the metal line.
FIG. 2 is a waveform diagram of a signal and its corresponding pre-emphasized signal.
Referring to FIG. 2, a pre-emphasized signal PE-Signal is defined as a signal of which the voltage at a rising edge and a falling edge are amplified. The signal is transmitted after the voltage at its edges is amplified. In this case, the voltage is amplified for only part of the entire period. Since the edges of the signal are amplified, the signal can have a sufficient amplitude required to be transmitted in practice within a period of signal transmission, even if the signal has a long settling time.
FIG. 3 illustrates an output circuit which performs an impedance matching function and a pre-emphasis function.
Referring to FIG. 3, an output circuit 300 includes an on-die termination (ODT) circuit 310 and a pre-emphasis circuit 320, 330.
The ODT circuit 310 includes a plurality of sub-cells having two P-type metal oxide semiconductor (MOS) transistors having gates which receive the same control signal and resistors which are respectively connected in series with the transistors. A second resistor R2 included in a sub-cell to which a second control signal C2 is applied has twice the resistance of a first resistor R1 included in a sub-cell to which a first control signal C1 is applied. A third resistor R3 included in a sub-cell to which a third control signal C3 is applied has twice the resistance of the second resistor R2. A fourth resistor R4 included in a sub-cell to which a fourth control signal C4 is applied has twice the resistance of the third resistor R3. In this manner, the control signals C1 to C4 are adjusted, and thus the output impedance can be adjusted in accordance with the resistors R1, R2, R3, R4 connected in parallel.
The pre-emphasis circuit 320, 330 amplifies the edge portions of the output signal by using signals PE-DI1 and PE-DI2 which have information on the portions at which signal transition occurs.
An output circuit 300 operates according to a first bias voltage Vb1 and a second bias voltage Vb2. When the output circuit 300 operates normally, signals DI1 and DI2 are transmitted to another chip or system.
In the conventional output circuit 300 of FIG. 3, the control signals C1 to C4 are generally obtained from a fuse circuit. Fusing is performed to match the output impedance with the characteristic impedance Zo of the metal line. Such fusing can only be performed a single time for each chip. Thus, after the output impedance is set, it cannot be altered. In addition, the MOS transistors of the pre-emphasis circuit 320, 330 to which the signals PE-DI1 and PE-DI2 are applied occupy a significantly large area on a layout.
The output circuit 300 is connected to all output terminals of a semiconductor chip. As described above, when the pre-emphasis circuit 320, 330 is connected to all of the output terminals, the semiconductor chip requires a larger area, and thus more power is consumed. In addition, since the output impedance is invariable, the output circuit 300 cannot actively cope with variation in the characteristic impedance Zo of the metal line, which occurs, for example, when the metal line is replaced.